The subject matter disclosed herein relates to an integrated circuit structure having a substantially planar N-P step height, and methods of forming such a structure.
In integrated circuits, particularly field effect transistors (FETs), utilizing high-k dielectric metal gates, silicon germanium (SiGe) has frequently been used as a channel material. During the process of SiGe growth and patterning in FET structures, the p-type FET (PFET) shallow trench isolation (STI) step height is often not co-planar (or, substantially level) with the n-type FET (NFET) STI. This height disparity can cause degraded performance in the FET and its corresponding integrated circuit structure.